IORQ: IO Request Input/Output Request
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it as IO request, input/output request.
In computing, input/output, or I/O, refers to the communication between an
information processing system (such as a computer), and the outside world –
possibly a human, or another information processing system. Inputs are the
signals or data received by the system, and outputs are the signals or data sent
from it. The term can also be used as part of an action; to "perform I/O" is to
perform an input or output operation. I/O devices are used by a person (or other
system) to communicate with a computer. For instance, keyboards and mouses are
considered input devices of a computer, while monitors and printers are
considered output devices of a computer. Devices for communication between
computers, such as modems and network cards, typically serve for both input and
output.
Note that the designation of a device as either input or output depends on the
perspective. Mouses and keyboards take as input physical movement that the human
user outputs and convert it into signals that a computer can understand. The
output from these devices is input for the computer. Similarly, printers and
monitors take as input signals that a computer outputs. They then convert these
signals into representations that human users can see or read. (For a human user
the process of reading or seeing these representations is receiving input.)
In computer architecture, the combination of the CPU and main memory (i.e.
memory that the CPU can read and write to directly, with individual
instructions) is considered the brain of a computer, and from that point of view
any transfer of information from or to that combination, for example to or from
a disk drive, is considered I/O. The CPU and its supporting circuitry provide
memory-mapped I/O that is used in low-level computer programming in the
implementation of device drivers.
Higher-level operating system and programming facilities employ separate, more
abstract I/O concepts and primitives. For example, most operating systems
provide application programs with the concept of files. The C and C++
programming languages, and operating systems in the Unix family, traditionally
abstract files and devices as streams, which can be read or written, or
sometimes both. The C standard library provides functions for manipulating
streams for input and output.
* Transput - In the context of the ALGOL 68 programming language, the input and
output facilities are collectively referred to as transput. The ALGOL 68
transput library recognizes the following standard files/devices: stand in,
stand out, stand error and stand back.
An alternative to special primitive functions is the I/O monad, which permits
programs to just describe I/O, and the actions are carried out outside the
program. This is notable because the I/O functions would introduce side-effects
to any programming language, but now purely functional programming is practical.
I/O Interface
I/O Interface is required whenever the I/O device is driven by the processor.
The interface must have necessory logic to interpret the device address
generated by the processor.
Handshaking should be implemented by the interface using appropriate commands
like (BUSY,READY,WAIT) the processor can communicate with I/O device through the
interface.
If incase different data formated being exchanged; interface must be ablt to
convert serial data to parallel form and vice-versa.
There must be provision for generating interrupts and the corresponding type
numbers for further processing by the processor if required
Contents
[hide]
* 1 Memory-mapped I/O
o 1.1 Addressing modes
+ 1.1.1 Direct addressing
+ 1.1.2 Indirect addressing
* 2 Port-mapped I/O
* 3 See also
[ Memory-mapped I/O
A computer that uses memory-mapped I/O accesses hardware by reading and writing
to specific memory locations, using the same assembler language instructions
that computer would normally use to access memory.
[ Addressing modes
There are many ways through which data can be read or stored in the memory. Each
method is an addressing mode, and has its own advantages and limitations.
There are many type of addressing modes such as direct addressing, indirect
addressing, immediate addressing, index addressing, based addressing,
based-index addressing, implied addressing, etc.
[ Direct addressing
In this type of address of the data is a part of the instructions itself. When
the processor decodes the instruction, it gets the memory address from where it
can be read/store the required information.
Mov Reg. [Addr]
Here the Addr operand points to a memory location which holds the data and
copies it into the specified Reg.
[ Indirect addressing
Here the address can be stored in a register. The instructions will have the
register which has the address. So to fetch the data, the instruction must be
decoded appropriate register selected. The contents of the register will be
treated as the address using this address appropriate memory location is
selected and data is read/written.
[ Port-mapped I/O
Port-mapped I/O usually requires the use of instructions which are specifically
designed to perform I/O operations.
Memory-mapped I/O (MMIO) and port I/O (also called port-mapped I/O or PMIO) are
two complementary methods of performing input/output between the CPU and
peripheral devices in a computer. Another method, not discussed in this article,
is using dedicated I/O processors—commonly known as channels on mainframe
computers—that execute their own instructions.
Memory-mapped I/O (not to be confused with memory-mapped file I/O) uses the same
address bus to address both memory and I/O devices, and the CPU instructions
used to access the memory are also used for accessing devices. In order to
accommodate the I/O devices, areas of CPU's addressable space must be reserved
for I/O rather than memory. The reservation might be temporary——the Commodore 64
could bank switch between its I/O devices and regular memory—or permanent. Each
I/O device monitors the CPU's address bus and responds to any CPU's access of
device-assigned address space, connecting the data bus to a desirable device's
hardware register.
Port-mapped I/O uses a special class of CPU instructions specifically for
performing I/O. This is generally found on Intel microprocessors, specifically
the IN and OUT instructions which can read and write a single byte to an I/O
device. I/O devices have a separate address space from general memory, either
accomplished by an extra "I/O" pin on the CPU's physical interface, or an entire
bus dedicated to I/O.
A device's direct memory access (DMA) is not affected by those CPU-to-device
communication methods, especially it is not affected by memory mapping. This is
because, by definition, DMA is a memory-to-device communication method, that
bypasses the CPU.
Hardware interrupt is yet another communication method between CPU and
peripheral devices. However, it is always treated separately for a number of
reasons. It is device-initiated, as opposed to above CPU-initiated methods. It
is also unidirectional, as information flows only from device to CPU. Lastly,
each interrupt line carries itself only one bit of information with a fixed
meaning, namely "there is an interrupt".
[ Relative merits of the two I/O methods
The main advantage of using port-mapped I/O is on CPUs with a limited addressing
capability. Because port-mapped I/O separates I/O access from memory access, the
full address space can be used for memory. It is also obvious to a person
reading an assembly language program listing when I/O is being performed, due to
the special instructions that can only be used for that purpose.
I/O operations can slow the memory access, if the address and data buses are
shared. This is because the peripheral device is usually much slower than main
memory. In some architectures, port-mapped I/O operates via a dedicated I/O bus,
alleviating the problem.[clarify]
The advantage of using memory-mapped I/O is that, by discarding the extra
complexity that port I/O brings, a CPU requires less internal logic and is thus
cheaper, faster and easier to build; this follows the basic tenets of reduced
instruction set computing, and is also advantageous in embedded systems. The
fact that regular memory instructions are used to address devices also means
that all of the CPU's addressing modes are available for the I/O as well as the
memory. As 16-bit peripherals have become obsolete and replaced with 32-bit and
64-bit in general use, reserving ranges of memory address space for I/O become
less of a problem.
[ Example
Consider a simple system built around an 8-bit microprocessor. Such a CPU might
provide 16-bit address lines, allowing it to address up to 64 kibibytes (KiB) of
memory. On such a system, perhaps the first 32 KiB of address space would be
allotted to random access memory (RAM), another 16K to read only memory (ROM)
and the remainder to a variety of other devices such as timers, counters, video
display chips, sound generating devices, and so forth. The hardware of the
system is arranged so that devices on the address bus will only respond to
particular addresses which are intended for them; all other addresses are
ignored. This is the job of the address decoding circuitry, and it is this that
establishes the memory map of the system.
Thus we might end up with a memory map like so:
Device Address range
(hexadecimal) Size
RAM 0000 - 7FFF 32 KiB
General purpose I/O 8000 - 80FF 256 bytes
Sound controller 9000 - 90FF 256 bytes
Video controller/text-mapped display RAM A000 - A7FF 2 KiB
ROM C000 - FFFF 16 KiB
Note that this memory map contains gaps; that is also quite common.
Assuming the fourth register of the video controller sets the background colour
of the screen, the CPU can set this colour by writing a value to the memory
location A003 using its standard memory write instruction. Using the same
method, glyphs can be displayed on a screen by writing character values into a
special area of RAM within the video controller. Prior to cheap RAM that enabled
bit-mapped displays, this character cell method was a popular technique for
computer video displays (see Text user interface).
[ Basic types of address decoding
* Exhaustive - 1:1 mapping of unique addresses to one hardware register
(physical memory location)
* Partial - n:1 mapping of n unique addresses to one hardware register. Partial
decoding allows a memory location to have more than one address, allowing the
programmer to reference a memory location using n different addresses. Synonyms:
foldback, multiply-mapped, partially-mapped.
* Linear - Address lines are used directly without any logic
[ Incomplete address decoding
Addresses may be decoded completely or incompletely by a device.
* Complete decoding involves checking every line of the address bus, causing an
open data bus when the CPU accesses an unmapped region of memory.
* Incomplete decoding, or partial decoding, uses simpler and often cheaper logic
that examines only some address lines. Such simple decoding circuitry might
allow a device to respond to several different addresses, effectively creating
virtual copies of the device at different places in the memory map. All of these
copies refer to the same real device, so there is no particular advantage in
doing this, except to simplify the decoder. Commonly, the decoding itself is
programmable, so the system can reconfigure its own memory map as required.
In computing, an interrupt is an asynchronous signal from hardware indicating
the need for attention or a synchronous event in software indicating the need
for a change in execution. A hardware interrupt causes the processor to save its
state of execution via a context switch, and begin execution of an interrupt
handler. Software interrupts are usually implemented as instructions in the
instruction set, which cause a context switch to an interrupt handler similar to
a hardware interrupt. Interrupts are a commonly used technique for computer
multitasking, especially in real-time computing. Such a system is said to be
interrupt-driven.
An act of interrupting is referred to as an interrupt request ("IRQ").
[ Overview
Hardware interrupts were introduced as a way to avoid wasting the processor's
valuable time in polling loops, waiting for external events.
Interrupts may be implemented in hardware as a distinct system with control
lines, or they may be integrated into the memory subsystem.
If implemented in hardware, an interrupt controller circuit such as the IBM PC's
Programmable Interrupt Controller (PIC) may be connected between the
interrupting device and to the processor's interrupt pin to multiplex several
sources of interrupt onto the one or two CPU lines typically available.
If implemented as part of the memory controller, interrupts are mapped into the
system's memory address space.
Interrupts can be categorized into: maskable interrupt (IRQ), non-maskable
interrupt (NMI), interprocessor interrupt (IPI), software interrupt, and
spurious interrupt.
* A maskable interrupt (IRQ) is a hardware interrupt that may be ignored by
setting a bit in an interrupt mask register's (IMR) bit-mask.
* Likewise, a non-maskable interrupt (NMI) is a hardware interrupt that does not
have a bit-mask associated with it - meaning that it can never be ignored. NMIs
are often used for timers, especially watchdog timers.
* An interprocessor interrupt is a special case of interrupt that is generated
by one processor to interrupt another processor in a multiprocessor system.
* A software interrupt is an interrupt generated within a processor by executing
an instruction. Software interrupts are often used to implement System calls
because they implement a subroutine call with a CPU ring level change.
* A spurious interrupt is a hardware interrupt that is unwanted. They are
typically generated by system conditions such as electrical interference on an
interrupt line or through incorrectly designed hardware.
Processors typically have an internal interrupt mask which allows software to
ignore all external hardware interrupts while it is set. This mask may offer
faster access than accessing an interrupt mask register (IMR) in a PIC, or
disabling interrupts in the device itself. In some cases, such as the x86
architecture, disabling and enabling interrupts on the processor itself acts as
a memory barrier, in which case it may actually be slower.
An interrupt that leaves the machine in a well-defined state is called a precise
interrupt. Such an interrupt has four properties:
* The Program Counter (PC) is saved in a known place.
* All instructions before the one pointed to by the PC have fully executed.
* No instruction beyond the one pointed to by the PC has been executed (That is
no prohibition on instruction beyond that in PC, it is just that any changes
they make to registers or memory must be undone before the interrupt happens).
* The execution state of the instruction pointed to by the PC is known.
An interrupt that does not meet these requirements is called an imprecise
interrupt.
The phenomenon where the overall system performance is severely hindered by
excessive amounts of processing time spent handling interrupts is called an
interrupt storm.
[ Types of Interrupts
[ Level-triggered
A level-triggered interrupt is a class of interrupts where the presence of an
unserviced interrupt is indicated by a high level (1), or low level (0), of the
interrupt request line. A device wishing to signal an interrupt drives the line
to its active level, and then holds it at that level until serviced. It ceases
asserting the line when the CPU commands it to or otherwise handles the
condition that caused it to signal the interrupt.
Typically, the processor samples the interrupt input at predefined times during
each bus cycle such as state T2 for the Z80 microprocessor. If the interrupt
isn't active when the processor samples it, the CPU doesn't see it. One possible
use for this type of interrupt is to minimize spurious signals from a noisy
interrupt line: a spurious pulse will often be so short that it is not noticed.
Multiple devices may share a level-triggered interrupt line if they are designed
to. The interrupt line must have a pull-down or pull-up resistor so that when
not actively driven it settles to its inactive state. Devices actively assert
the line to indicate an outstanding interrupt, but let the line float (do not
actively drive it) when not signalling an interrupt. The line is then in its
asserted state when any (one or more than one) of the sharing devices is
signalling an outstanding interrupt.
This class of interrupts is favored by some because of a convenient behavior
when the line is shared. Upon detecting assertion of the interrupt line, the CPU
must search through the devices sharing it until one requiring service is
detected. After servicing this device, the CPU may recheck the interrupt line
status to determine whether any other devices also need service. If the line is
now deserted, the CPU avoids checking the remaining devices on the line. Since
some devices interrupt more frequently than others, and other device interrupts
are particularly expensive, a careful ordering of device checks is employed to
increase efficiency.
There are also serious problems with sharing level-triggered interrupts. As long
as any device on the line has an outstanding request for service the line
remains asserted, so it is not possible to detect a change in the status of any
other device. Deferring servicing a low-priority device is not an option,
because this would prevent detection of service requests from higher-priority
devices. If there is a device on the line that the CPU does not know how to
service, then any interrupt from that device permanently blocks all interrupts
from the other devices.
The original PCI standard mandated shareable level-triggered interrupts. The
rationale for this was the efficiency gain discussed above. (Newer versions of
PCI allow, and PCI Express requires, the use of message-signalled interrupts.)
[ Edge-triggered
An edge-triggered interrupt is a class of interrupts that are signalled by a
level transition on the interrupt line, either a falling edge (1 to 0) or a
rising edge (0 to 1). A device wishing to signal an interrupt drives a pulse
onto the line and then releases the line to its quiescent state. If the pulse is
too short to be detected by polled I/O then special hardware may be required to
detect the edge.
Multiple devices may share an edge-triggered interrupt line if they are designed
to. The interrupt line must have a pull-down or pull-up resistor so that when
not actively driven it settles to one particular state. Devices signal an
interrupt by briefly driving the line to its non-default state, and let the line
float (do not actively drive it) when not signalling an interrupt. This type of
connection is also referred to as open collector. The line then carries all the
pulses generated by all the devices. However, interrupt pulses from different
devices may merge if they occur close in time. To avoid losing interrupts the
CPU must trigger on the trailing edge of the pulse (e.g., the rising edge if the
line is pulled up and driven low). After detecting an interrupt the CPU must
check all the devices for service requirements.
Edge-triggered interrupts do not suffer the problems that level-triggered
interrupts have with sharing. Service of a low-priority device can be postponed
arbitrarily, and interrupts will continue to be received from the high-priority
devices that are being serviced. If there is a device that the CPU does not know
how to service, it may cause a spurious interrupt, or even periodic spurious
interrupts, but it does not interfere with the interrupt signalling of the other
devices. However, it is fairly easy for an edge triggered interrupt to be missed
- for example if interrupts have to be masked for a period - and unless there is
some type of hardware latch that records the event it is impossible to recover.
Such problems caused many "lockups" in early computer hardware because the
processor didn't know it was expected to do something. More modern hardware
often has one or more interrupt status registers that latch the interrupt
requests; well written edge-driven interrupt software often checks such
registers to ensure events are not missed.
The elderly ISA bus uses edge-triggered interrupts, but does not mandate that
devices be able to share them. The parallel port also uses edge-triggered
interrupts. Many older devices assume that they have exclusive use of their
interrupt line, making it electrically unsafe to share them. However, ISA
motherboards include pull-up resistors on the IRQ lines, so well-behaved devices
share ISA interrupts just fine.
[ Hybrid
Some systems use a hybrid of level-triggered and edge-triggered signalling. The
hardware not only looks for an edge, but it also verifies that the interrupt
signal stays active for a certain period of time.
A common use of a hybrid interrupt is for the NMI (non-maskable interrupt)
input. Because NMIs generally signal major – or even catastrophic – system
events, a good implementation of this signal tries to ensure that the interrupt
is valid by verifying that it remains active for a period of time. This 2-step
approach helps to eliminate false interrupts from affecting the system.
[ Message-signalled
A message-signalled interrupt does not use a physical interrupt line. Instead, a
device signals its request for service by sending a short message over some
communications medium, typically a computer bus. The message might be of a type
reserved for interrupts, or it might be of some pre-existing type such as a
memory write.
Message-signalled interrupts behave very much like edge-triggered interrupts, in
that the interrupt is a momentary signal rather than a continuous condition.
Interrupt-handling software treats the two in much the same manner. Typically,
multiple pending message-signalled interrupts with the same message (the same
virtual interrupt line) are allowed to merge, just as closely-spaced
edge-triggered interrupts can merge.
Message-signalled interrupt vectors can be shared, to the extent that the
underlying communication medium can be shared. No additional effort is required.
Because the identity of the interrupt is indicated by a pattern of data bits,
not requiring a separate physical conductor, many more distinct interrupts can
be efficiently handled. This reduces the need for sharing. Interrupt messages
can also be passed over a serial bus, not requiring any additional lines.
PCI Express, a serial computer bus, uses message-signalled interrupts
exclusively.
[ Difficulty with sharing interrupt lines
Multiple devices sharing an interrupt line (of any triggering style) all act as
spurious interrupt sources with respect to each other. With many devices on one
line the workload in servicing interrupts grows as the square of the number of
devices. It is therefore preferred to spread devices evenly across the available
interrupt lines. Shortage of interrupt lines is a problem in older system
designs where the interrupt lines are distinct physical conductors. Message-signalled
interrupts, where the interrupt line is virtual, are favoured in new system
architectures (such as PCI Express) and relieve this problem to a considerable
extent.
Some devices with a badly-designed programming interface provide no way to
determine whether they have requested service. They may lock up or otherwise
misbehave if serviced when they do not want it. Such devices cannot tolerate
spurious interrupts, and so also cannot tolerate sharing an interrupt line. ISA
cards, due to often cheap design and construction, are notorious for this
problem. Such devices are becoming much rarer, as hardware logic becomes cheaper
and new system architectures mandate shareable interrupts.
Typical uses
Typical uses of interrupts include the following: system timers, disks I/O,
power-off signals, and traps. Other interrupts exist to transfer data bytes
using UARTs or Ethernet; sense key-presses; control motors; or anything else the
equipment must do.
A classic system timer interrupt interrupts periodically from a counter or the
power-line. The interrupt handler counts the interrupts to keep time. The timer
interrupt may also be used by the OS's task scheduler to reschedule the
priorities of running processes. Counters are popular, but some older computers
used the power line frequency instead, because power companies in most Western
countries control the power-line frequency with a very accurate atomic clock.
A disk interrupt signals the completion of a data transfer from or to the disk
peripheral. A process waiting to read or write a file starts up again.
A power-off interrupt predicts or requests a loss of power. It allows the
computer equipment to perform an orderly shutdown.
Interrupts are also used in typeahead features for buffering events like
keystrokes.
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